This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-281398, filed Sep. 17, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a circuit configuration which reduces a stand-by current in a memory-embedded logic LSI.
2. Description of the Related Art
Heretofore, chips have been constituted separately in accordance with several functions, but a semiconductor integrated circuit called a system LSI (large scale integrated circuit) in which the functions are integrated into one chip has become important. Of the system LSIs, a memory-embedded logic LSI in which a memory circuit is embedded into a logic LSI has particularly been drawing attention and recently developed.
This kind of memory-embedded logic LSI is applied to a digital civil-use appliance such as a portable appliance, a mobile product, and so it has an important theme of reducing power dissipation in its use.
Needless to say, it is important that the memory-embedded logic LSI is low in power dissipation during its use, but in addition, it is also important to reduce stand-by power dissipation, to which much attention has recently been paid.
FIG. 5 is a block diagram showing a conventional memory-embedded logic LSI501, which is divided into a logic unit 502 and a memory macro 503. Furthermore, the memory macro 503 includes therein an internal potential generation circuit group 504 which is used for the memory macro 503.
A stand-by current of the memory macro 503 is mainly dissipated by the internal potential generation circuit group 504, which generates a potential used in the memory macro 503. The internal potential generation circuit group 504 is comprised of a word line drive internal step-up circuit 508 used as an internal power supply of the memory macro 503, an internal step-down potential generation circuit 509, a substrate potential generation circuit 512 for feeding a substrate potential and a well potential, a reference potential generation circuit 507 used as an internal reference potential, and the like.
The word line drive internal step-up circuit 508 is used, for example, as a power supply for driving a word line or a power supply for driving a gate signal of a transistor which controls an interconnection between a pair of a sense-amplifier and a bit line in a shared sense-amplification system.
The internal step-down potential generation circuit 509 is used as a power supply for generating a voltage lower than an external power supply voltage in the memory macro 503 thereby to pre-charge a bit line, or as a power supply for feeding a plate potential for a memory cell.
The reference potential generation circuit 507 is a circuit for generating a reference potential for potentials generated by the other internal voltage generation circuits, and as the reference potential generation circuit 507, there is used a circuit having a low temperature dependency and external voltage dependency.
Upon application of power, the internal potential generation circuit group 504 generates, for a certain time, a reset signal which initializes an internal circuit (not shown) in the memory macro 503, for example, a flip-flop, a latch, a register, etc., and it is possible that each internal potential is generated according to a signal which keeps a certain potential level at an operating voltage by an external voltage and which is output from an external power supply voltage detection circuit 506. Therefore, the internal potential generation circuit group 504 is controlled by a power-on sequence control circuit 505 so as to prevent the occurrence of latch-up and the like during the generation of the internal potentials.
In the memory macro 503 of the conventional memory-embedded logic LSI 501, however, the internal potential generation circuit group 504 uses therein a number of comparators and resistors for controlling their respective potentials at predetermined levels, so that these circuits always consume a current of a few tens of micro-amperes in a state where the internal potential can be generated. This electric current increases the current consumption during the stand-by. Conventionally, to suppress the stand-by current consumption of the memory macro 503, there has been no way but to turn off the external power supply fed to the memory macro 503, in which case the operations of the logic circuit 502 have all been stopped except the memory macro 503.
A first aspect of the present invention, there is provided a semiconductor integrated circuit which comprises an internal potential generation circuit for a memory; a current flow pass interruption circuit connected to the internal potential generation circuit; and an input terminal, connected to the current flow pass interruption circuit, for providing a stand-by setting signal controlling the current flow pass interruption circuit, wherein a potential is supplied to the internal potential generation circuit during the operation of the memory, and it is interrupted during the stand-by of the memory to supply the potential to the internal potential generation circuit.
A second aspect of the present invention, there is provided a semiconductor integrated circuit which comprises a plurality of internal potential generation circuits for a memory; a current flow pass interruption circuit connected to each of the plurality of internal potential generation circuits; and an input terminal connected to each of the current flow pass interruption circuits, for providing a stand-by setting signal to control the current flow pass interruption circuits, wherein a potential is supplied to the plurality of internal potential generation circuits during the operation of the memory, and it is interrupted during the stand-by of the memory to supply the potential to the plurality of internal potential generation circuits.
A third aspect of the present invention, there is provided a semiconductor integrated circuit which comprises an internal potential generation circuit for a memory; a current flow pass interruption circuit connected to the internal potential generation circuit; a power-on sequence control circuit connected to the internal potential generation circuit; an external power supply voltage detection circuit for detecting an external power supply to output a detection signal; an LPM reset circuit connected to the external power supply voltage detection circuit, the power-on sequence control circuit and the internal potential generation circuit, respectively; and an input terminal connected to the LPM reset circuit, wherein an LPM reset signal is produced in the LPM reset circuit by at least two signals selected from the group consisting of the detection signal, a stand-by setting signal input from the input terminal and a signal output from the power-on sequence control circuit and specifying an operable state of the memory, and in accordance with the LPM reset signal, a potential is supplied from a power supply to the internal potential generation circuit during the operation of the memory and it is interrupted during the stand-by of the memory to supply the potential from the power supply to the internal potential generation circuit.